Present day semi-conductors in commercial use are almost exclusively manufactured with optical lithography techniques for pattern transfer. To satisfy the demand for ever increasing density and corresponding reduction of line width, two general approaches are available; using non-light lithography, or the innovation of new manufacturing techniques for increasing the density of integrated circuitry with the use of optical lithography techniques.
Much effort has gone into the former approach, see for example "High Speed MOS FET Circuits Using Advanced Lithography" in Computer, Volume 9, No. 2, February 1976, pages 31-37, which describes the substantial equipment cost and complexities of X-ray and electron beam lithography.
Present day optical techniques are considered suitable for commercial production of devices having dimensions of at least one micrometer, and it is an object of the invention to provide a technique for the fabrication of a high speed dynamic RAM in which it is important to achieve delineation substantially less than one micrometer, and wherein this is achieved using optical lithography.
A relatively recent addition to the arsenal of tools available in the manufacture of integrated circuitry is plasma or reactive ion etching (sometimes referred to herein as RIE). This is a technique which has been developed for etching metals, semi-conductor materials and dielectrics in the manufacture of integrated circuit devices. The process involves the use of a plasma or ionized gas containing a variety of highly reactive particles such as ions, free electrons and free radicals. The plasma used in etching may be maintained in relatively low temperatures on the order of 250.degree. C. at low pressures, in the range of 0.005 to 20 torr. See in this regard "A Survey of Plasma Etching Processes" by Bersin in Solid State Technology, May 1976, pages 31-36, Hochberg U.S. Pat. No. 3,966,577; Bondur U.S. Pat. Nos. 4,104,086 and 4,139,442. Further information concerning reactive ion etching can be found in the Harvilchuck patent application Ser. No. 960,322 filed Nov. 13, 1978, assigned to the assignee of this application. An example of the use of reactive ion etching in another semi-conductor device is found in Ho U.S. Pat. No. 4,209,349; assigned to the assignee of this application.
A particularly effective MOS FET configuration allowing densities higher than that heretofore available in such devices is described in "A New Short Channel MOS FET with Lightly Doped Drain" by Saito et al in Denshi Tsushin Rengo Taikai (Japanese) April 1978, page 2-20. The LDD N MOS FET includes, in addition to the channel separating implanted N.sup.+ source and drain regions, diffused N.sup.- regions, which increases the channel breakdown voltage or snap-back voltage and reduces device drain junction electron impact ionization (and thus, hot electron emission) by spreading the high electric field at the drain pinch-off region into the N.sup.- region. This allows either an increase in power supply voltage or reduction in channel length at a given voltage to achieve performance enhancement. Insofar as applicants are informed, the known techniques for fabricating such a device generally include using planar silicon gate processing techniques and optical lithography in which first, a gate stack is patterned, and the N.sup.+ source/drain regions are implanted. Following this, an etch is used to undercut the polysilicon gate, and the N.sup.- region is implanted in the undercut region. Controlling the extent of undercut is difficult because of the small tolerance required on the length of the N.sup.- region. It is another object of the present invention, therefore, to provide a method of fabricating an LDD MOSFET which provides for readily achievable control on the length of the N.sup.- regions especially where those regions are substantially less than 1 micrometer long.
Other features, objects and advantages of the invention will be apparent as this description proceeds.